The present invention relates to integrated circuit fabrication and, more particularly, to sputter deposition systems. A major objective of the present invention is to provide for improved yields and throughput for submicron processing technologies.
Much of modern progress is associated with the increasing miniaturization of integrated circuits made possible by advances in semiconductor processing technology. Specifically, the miniaturization has been made possible as photolithographic techniques have permitted smaller features to be defined. Not long ago, 2 and 3 micron features were the minimum; today, state-of-the-art procedures permit submicron features to be defined.
In a typical fabrication method, transistor active regions are defined by doping a silicon substrate. Local interconnects and gates (for MOS technology) are defined by patterning polysilicon over the substrate. Devices so defined are integrated by a metal interconnect structure. This metal interconnect structure is typically insulated from the underlying transistors by a silicon dioxide layer. Metal vias, e.g., tungsten-titanium barrier and aluminum-copper conductors, can extend through the insulator to provide the desired electrical connections between the metal interconnect structure and the underlying transistors.
The metal vias can be formed by opening apertures through the insulator and sputtering metal so that the via apertures are filled. Sputtering involves bombarding a target of the material to be deposited with ions from a heavy gas plasma. Through momentum transfer, atoms near the surface of the target material are ejected. Atoms having a suitable trajectory are deposited on the wafer on which integrated circuits are being defined.
Generally, the sputtered atoms are deposited on the top surface of the wafer, at the base of apertures, and on aperture sidewalls. Material deposited on the aperture sidewalls can occlude the aperture base. This occlusion is negligible when the aperture aspect ratio, i.e., the ratio of the aperture height to the aperture cross section, is small. However, to achieve maximal circuit densities, aperture cross sections have decreased to the extent permitted by advances in photolithography. Aperture heights are bounded from below by the requirements for forming a satisfactory insulator layer. Thus, aspect ratios have been increasing to the point where sidewall depositions can prevent satisfactory electrical connections at the aperture base.
This problem is addressed by minimizing sidewall depositions until sufficient material has been deposited on the aperture base, effectively lowering the aperture aspect ratio. Sidewall depositions can be minimized by collimating the material approaching the wafer. To this end, a grating is interposed between the sputter target and the wafer. Atoms with oblique trajectories are captured by the grating, while most of the atoms with trajectories orthogonal to the wafer are allowed to reach the wafer. The orthogonal trajectory that allows atoms through the grating also favors deposition at the aperture bases as opposed to the aperture sidewalls. Thus, adequate electrical contacts at the via aperture bases are formed.
Collimation filters out many atoms that would otherwise be deposited on the wafer, and thus adversely affects the deposition rate. More time is required to achieve a desired deposition thickness so that processing throughput is reduced. This throughput reduction adds substantially to the cost of the completed integrated circuit. To enhance throughput, collimated sputtering can be terminated once aperture aspect ratios are sufficiently reduced that the sidewall occlusion resulting from subsequent uncollimated sputtering would not be a problem. The wafer is then transferred to a sputter chamber without a collimator for a relatively rapid completion of the deposition.
Each transfer between chambers incurs its own delay and risks of wafer breakage and contamination. These problems are minimized by multi-chamber machines that provide for automated and sealed wafer transfers. However, the number of chambers per machine is limited so at some point an addition transfer requires a transfer between machines. These intermachine transfers are more time consuming and more prone to contamination and breakage.
While the increased throughput of a two-step sputter deposition can outweigh the disadvantages of the additional transfer, it would be desirable to obtain the advantages with reduced tradeoffs. What is needed is a sputtering system that provides satisfactory aperture base coverage and reasonable sputtering throughput, while minimizing wafer transfers.